2005 International Conference on
Compilers, Architectures and Synthesis
of Embedded Systems (CASES�05)

The Sir Francis Drake Hotel, San Francisco, CA, USA
Sept. 24 � Sept. 27, 2005

Advance Program

Main Conference Program

Sunday, Sept. 25

�8:45 -� 9:00  Welcome

Tom Conte, Paolo Faraboschi

�9:00 � 10:00  Keynote Presentation

Introduction: Paolo Faraboschi

�����

������ How Compilers and Tools Differ for Embedded Systems. [abstract]

�Michael Wolfe, STMicroelectronics

10:00 � 10:30  Coffee Break

10:30 - 12:30  Session 1: Hardware Specialization

Session Chair: Eric Debes, Intel

� Exploiting Pipelining to Relax Register-File Port Constraints of Instruction-Set Extensions

��� Laura Pozzi, Ecole Polytechnique F�d�rale de Lausanne (EPFL)

��� Paolo Ienne, Ecole Polytechnique F�d�rale de Lausanne (EPFL)

� Exploring the Design Space of LUT-based Transparent Accelerators

��� Sami Yehia, ARM Ltd.

��� Nathan T Clark, University of Michigan

��� Scott A Mahlke, University of Michigan

��� Krisztian Flautner, ARM Ltd.

� Automating Custom-Precision Function Evaluation for Embedded Processors

��� Ray C.C. Cheung, Imperial College London

��� Dong-U Lee, UCLA

��� Oskar Mencer, Imperial College London

��� Wayne Luk, Imperial College London

��� Peter Y.K. Cheung, Imperial College London

� Energy Management for Commodity Short-Bit-Width Microcontrollers

��� Rony Ghattas, North Carolina State University

��� Alexander G. Dean, North Carolina State University

12:30 -� 1:30  Lunch

�1:30 -� 3:30  Session 2: Security

Session Chair: Krisztian Flautner, ARM

� Anomalous Path Detection with Hardware Support

��� Tao Zhang, Georgia Institute of Technology

��� Xiaotong Zhuang, Georgia Institute of Technology

��� Santosh Pande, Georgia Institute of Technology

��� Wenke Lee, Georgia Institute of Technology

� Hardware Support for Code Integrity in Embedded Processors

��� Milena Milenkovic, WBI Performance II, IBM

��� Aleksandar Milenkovic, The University of Alabama in Huntsville

��� Emil Jovanov, The University of Alabama in Huntsville

� Segment Protection for Embedded Systems Using Run-time Checks

��� Matthew Stephen Simpson, University of Maryland

��� Bhuvan Middha, University of Maryland

� ��Rajeev Kumar Barua, University of Maryland

� SECA: Security-Enhanced Communication Architecture

��� Joel Coburn, NEC Laboratories America

��� Srivaths Ravi, NEC Laboratories America

��� Anand Raghunathan, NEC Laboratories America

��� Srimat Chakradhar, NEC Laboratories America

�3:30 �� 4:00  Coffee Break

�4:00 -� 6:00  Session 3: Memories

Session Chair: Al Davis, U. Utah

� Compilation Techniques for Energy Reduction in Horizontally Partitioned Cache Architectures

��� Aviral Shrivastava, University of California, Irvine

��� Ilya Issenin, University of California, Irvine

��� Nikil Dutt, University of California, Irvine

� A Post-Compilation Register Reassignment Technique for Improving Hamming Distance Code Compression

��� Montserrat B Ros, The University of New England

��� Peter Sutton, The University of Queensland

� Verifiable Annotations for Embedded Java Environments

��� Guangyu Chen Chen, Pennsylvania State University

��� Mahmut Kandemir, Pennsylvania State University

� Memory Allocation for Embedded Systems with a Compile-Time-Unknown Scratch-Pad Size

��� Nghi B. Nguyen, University of Maryland

��� Angel� Dominguez, University of Maryland

��� Rajeev� Barua, University of Maryland

Monday, Sept. 26

�9:00 � 10:00  Invited Talk

Introduction: Tom Conte

������ Embedded Benchmarking. [abstract]

�Markus Levy, EEMBC

10:00 � 10:30  Coffee Break

10:30 - 12:30  Session 4: Compilation

Session Chair: Laura Pozzi, EPFL Lausanne

� Optimizing Stream Programs Using Linear State Space Analysis

��� Sitij Agrawal, Massachusetts Institute of Technology

��� William Thies, Massachusetts Institute of Technology

��� Saman Amarasinghe, Massachusetts Institute of Technology

� Compiler-Directed Proactive Power Management for Networks

��� Feihui Li, Dept of CSE, the Pennsylvania State University

��� Guangyu Chen, Dept of CSE, the Pennsylvania State University

��� Mahmut Kandemir, Dept of CSE, the Pennsylvania State University

��� Mary Jane Irwin, Dept of CSE, the Pennsylvania State University

� Equivalence Checking of Arithmetic Expressions using Fast Evaluation

��� Mohammad Ali Ghodrat, University of California Irvine

��� Tony Givargis, University of California Irvine

��� Alex Nicolau, University of California Irvine

� Single Appearance Schedule with Dynamic Loop Count for Minimum Data Buffer from Synchronous Dataflow Graphs

��� Hyunok Oh, Center for Embedded Computer Systems, UC Irvine

��� Nikil Dutt, Center for Embedded Computer Systems, UC Irvine

��� Soonhoi Ha, EECS, Seoul National University

12:30 -� 1:30  Lunch

�1:30 -� 3:30  Session 5: Operating Systems

Session Chair: Jaime Moreno, IBM Research

� Architectural Support for Real-Time Task Scheduling in SMT Processors

��� Francisco J. Cazorla, Universitat Politecnica de Catalunya

��� Peter M.W. Knijnenburg, LIACS, Leiden University

��� Rizos Sakellariou, University of Manchester

��� Enrique Fernandez, University of Las Palmas de Gran Canria

��� Alex Ramirez, Universitat Politecnica de Catalunya

��� Mateo Valero, Universitat Politecnica de Catalunya

� Intra-task Scenario-aware Voltage Scheduling

��� Stefan Valentin Gheorghita, Eindhoven University of Technology, EE Dept.

��� Twan Basten, Eindhoven University of Technology, EE Dept.

��� Henk Corporaal, Eindhoven University of Technology, EE Dept.

� Energy Aware Kernel for Hard Real-Time Systems

��� A Goel, University of Massachusetts

��� C M Krishna, University of Massachusetts

��� I Koren, University of Massachusetts

� MTSS: Multi Task Stack Sharing for Embedded Systems

��� Bhuvan Middha, Dept. of Electrical and Computer Eng., Univ. of Maryland

��� Matthew Simpson, Dept. of Electrical and Computer Eng., Univ. of Maryland

��� Rajeev Barua, Dept. of Electrical and Computer Eng., Univ. of Maryland

�3:30 �� 4:00  Coffee Break

�4:00 -� 6:00  Session 6: Architecture

Session Chair: Tony Givargis, U. C. Irvine

� The Microarchitecture of FPGA-Based Soft Processors}

��� Peter Yiannacouras, University of Toronto

��� Jonathan� Rose, University of Toronto

��� J. Gregory Steffan, University of Toronto

� Virtual Multiprocessor: An Analyzable, High-Performance Microarchitecture for Real-Time Computing

��� Ali El-Haj-Mahmoud, ECE Department, North Carolina State University

��� Ahmed� S. AL-Zawawi, ECE Department, North Carolina State University

��� Aravindh Anantaraman, ECE Department, North Carolina State University

��� Eric Rotenberg, ECE Department, North Carolina State University

� An Esterel Processor with Full Preemption Support and its Worst Case Reaction Time Analysis

��� Xin Li, Christian-Albrechts-Universit�t zu Kiel

��� Jan Lukoschus, Christian-Albrechts-Universit�t zu Kiel

��� Marian Boldt, Christian-Albrechts-Universit�t zu Kiel

��� Michael Harder, Christian-Albrechts-Universit�t zu Kiel

��� Reinhard von Hanxleden, Christian-Albrechts-Universit�t zu Kiel

� Fast and Fair: Data-stream Quality of Service

��� Thomas Y. Yeh, Department of Computer Science, UCLA

��� Glenn Reinman, Department of Computer Science, UCLA

Tuesday, Sept. 27

��8:30 - 10:30  Session 7: Communication Systems

Session Chair: Alex Dean, NC State U.

� A Second-Generation Sensor Network Processor with Application-Driven Memory Optimizations and Out-of-Order Execution

��� Leyla� Nazhandali, University of Michigan

��� Michael Minuth, University of Michigan

��� Bo Zhai, University of Michigan

��� Javin Olson, University of Michigan

��� Todd Austin, University of Michigan

��� David Blaauw, University of Michigan

� A DualProcessor Solution for the MAC Layer of a Software Defined Radio Terminal

��� Hyunseok Lee, University of Michigan

��� Trevor Mudge, University of Michigan

� Instruction Set Extensions for Software Defined Radio on a Multithreaded Processor

��� Suman� Mamidi, University of Wisconsin

��� Emily R Blem, University of Wisconsin

��� Michael� J Schulte, University of Wisconsin

��� John Glossner, Sandbridge Technologies

��� Daniel� Iancu, Sandbridge Technologies

��� Andrei Iancu, Sandbridge Technologies

��� Mayan Moudgill, Sandbridge Technologies

��� Sanjay Jinturkar, Sandbridge Technologies

� Software-Directed Power-Aware Interconnection Networks

��� Vassos Soteriou, Princeton University

��� Noel Eisley, Princeton University

��� Li-Shiuan Peh, Princeton University

�10:30 �� 11:00  Coffee Break

�11:00 -� 12:30  Session 8: Threads (and more)

Session Chair: Rajeev Barua, U. Maryland

� Balancing Register Pressure and Context-Switching Delays in ASTI Systems

��� Siddhartha� Shivshankar, North Carolina State University

��� Sunil Vangara, North Carolina State University

��� Alexander G. Dean, North Carolina State University

� Developing Embedded Multi-threaded Applications with CATAPULTS, a Domain-specific Language for Generating Thread Schedulers

��� Matthew D Roper, Dept. of Computer Science, University of California, Davis

��� Ronald A Olsson, Dept. of Computer Science, University of California, Davis

� Micro Embedded Monitoring for Security in Application Specific Instruction-set Processors

��� Roshan G Ragel, University of New South Wales, National ICT Australia

��� Sri Parameswaran, University of New South Wales, National ICT Australia

��� Sayed Mohammad Kia, Abbaspour University

�12:30 -� 12:40  Closing, best paper award